1. Field of Invention
The present invention relates to a method of forming and operating a non-volatile flash memory cell structure. More particularly, the present invention relates to a method of forming and operating a trench split gate non-volatile flash memory cell structure.
2. Description of Related Art
In recent years, the need for non-volatile memory has increased at a rapid rate due to the exponential growth of portable electronic product markets. As technologies for manufacturing flash memories improve, unit cost is greatly reduced stimulating a wider application. Digital cameras, electronic organizers, MP3, electronic answering machines and programmable integrated circuits (IC) often depend on flash memory for data storage.
Most flash memory is designed as a type of electrically programmable read-only-memory (EPROM) having an N-channel memory unit. Programming is conducted using channel hot electrons. Among various types of flash memory units, split gate structure has the best hot electron programming efficiency. A conventional stacked flash memory using a channel hot electron injection mechanism or a flash memory using a channel initiated secondary electron injection mechanism through the application of a negative bias voltage on substrate has a hot electron injection efficiency (gate current over drain current) for programming, around 10xe2x88x926xcx9c10xe2x88x928. However, a split gate flash memory using a source side injection (SSI) hot electron programming mechanism can reach an efficiency of 10xe2x88x924xcx9c10xe2x88x926.
FIG. 1 is a schematic cross-sectional view of a conventional split-gate flash memory unit. This type of split-gate flash memory is also referred to as a sidewall select-gate on the source side (SISOS). To program the split-fate flash memory, a voltage VCG=17V is applied to the control gate 10, a voltage VD=5V is applied to the drain terminal 12 and a voltage Vs=Vsub=0V is applied to the source terminal 14 and the substrate 16. In addition, a voltage VSWG=2V is applied to the select gate terminal 18 so that a 5V voltage differential is formed between the source terminal 14 and the neighborhood of node A. Hence, electron injection is boosted and electrons are channeled into interior of the floating gate 20 through the voltage VCG=17V applied to the control gate terminal 10. The select gate terminal 18 is capable of controlling the electric field created between the source terminal 14 and the node A so that electron injection efficiency is effectively raised. To conduct an erasure, a voltage VD=14V is applied to the drain terminal 12 while other contact points remain at 0V. Therefore, electrons within the floating gate 20 drain away via the drain terminal 12.
Although the aforementioned split-gate flash memory structure has a relatively high efficiency, each memory unit needs to occupy a larger surface area due to the incorporation of a select gate over the source terminal. Thus, each split-gate memory unit occupies more area than a conventional flash memory unit leading to a lowering of packing density and memory capacity. Furthermore, the injection of electrons into the floating gate after crossing over the select gate relies on the hot electrons created by the high electric field at the gap due to a high voltage between the select gate and the floating gate. Rather than focusing at the floating gate, the accelerated electrons focus upon the underlying depletion layer created by the floating gate and the drain voltage. Hence, unless a very high voltage at the gate terminal and a matching drain voltage are applied so that the accelerated electrons converge upon the floating gate region, only a minority of electrons will ultimately end up inside the floating gate.
Accordingly, one object of the present invention is to provide a method of forming and operating a trench split-gate non-volatile flash memory structure. Area occupation of the select gate and the source terminal inside a trench split-gate non-volatile flash memory cell relative to the entire cell is reduced and hence packing density of the memory is increased. Furthermore, the trench split-gate non-volatile flash memory cell structure is also specially fabricated to inject most accelerated electrons into the floating gate and hence operating efficiency of the memory is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a trench split-gate non-volatile flash memory cell structure. The structure comprises a P-type substrate, a deep N-well layer, a shallow P-well layer, a source region, a trench auxiliary gate region, a gate region and a drain region. The P-type substrate, the deep N-well layer and the shallow P-well layer are arranged into a stack with P-type substrate at the bottom, the deep N-well layer in the middle and the shallow P-well layer on top. The source region is embedded inside the deep N-well layer. The trench auxiliary gate region is embedded within the deep N-well layer and the shallow P-well layer above the source region. The gate region is above the shallow P-well layer on one side of the auxiliary gate region. The drain region is embedded within the P-well layer on one side of the gate region. In addition, a metal silicide layer covers the exposed drain region and the trench auxiliary gate region.
The trench auxiliary gate includes a polysilicon layer and an oxide layer at the bottom and each side of the polysilicon layer. The gate includes a first polysilicon layer, a second polysilicon layer above the first polysilicon layer and an isolation layer between the first and the second polysilicon layer and on the sidewalls of the first polysilicon layer. The isolation layer can be an oxide-nitride-oxide (ONO) layer, an oxide-nitride (ON) layer or a nitride (N) layer.
This invention also provides a method of forming trench split-gate non-volatile flash memory cells that include the following steps. First, a P-type substrate is provided. A deep N-well layer is formed in the P-type substrate and a shallow P-well layer is formed over the deep N-well layer. A gate region is formed over the P-well layer and a drain region and an auxiliary gate region are formed on each side of the gate region. A spacer is formed on each side of the gate region. A trench is formed in the deep N-well layer and the shallow P-well layer within the auxiliary gate region. An oxide layer is formed inside the trench. The deep N-well layer and the drain region of the P-well layer underneath the trench are heavily doped to form a source terminal and a drain terminal. A first polysilicon layer is deposited over the gate region to form a floating gate. An isolation layer is formed over the first polysilicon layer, the drain region and the trench. A second polysilicon layer is formed over the isolation layer to form a control gate. Furthermore, a metal silicide layer may form over the exposed drain terminal and the trench auxiliary gate after the formation of the trench auxiliary gate. Hence, resistance between the auxiliary gate and the drain terminal is lowered, thereby increasing reading current and lowering RC delay.
This invention also provides a method of operating a trench split-gate non-volatile flash memory cell. A word line voltage, a source voltage, an auxiliary gate voltage and a bit line voltage are applied to the gate region, the source region, the trench auxiliary gate and the drain region respectively. The bottom section of the flash memory cell structure includes, from top to bottom, a shallow P-well layer, a deep N-well layer and a P-type substrate. The source region is embedded within the deep N-well layer and the trench auxiliary gate region is above the source region embedded within the shallow P-well layer and the deep N-well layer. The operation method includes the following steps.
To conduct a programming operation, a high voltage is applied to the word line. A voltage lower than the word line voltage is applied to the bit line. A voltage lower than both the word line voltage as well as the bit line voltage is applied to the source terminal. A voltage lower than both the word line voltage and the bit line voltage is applied to the auxiliary gate terminal.
To conduct an erasing operation, a low voltage is applied to the word line. A voltage higher than the word line voltage is applied to the bit line. A voltage higher than the word line voltage but lower than the bit line voltage is applied to the source terminal. A voltage higher than the word line voltage but lower than the bit line voltage is applied to the auxiliary gate terminal.
To conduct a reading operation, a higher voltage is applied to the word line and a voltage lower than the word line voltage is applied to the source terminal. A voltage higher than the source terminal voltage is applied to the bit line. Similarly, a voltage higher than the source terminal is also applied to the auxiliary gate terminal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.